Partner 1Partner 2AreaTitle
Chen, T-YZege, ABenchmarking Performance Modelling of Parallel SVD Code
Chenney, SMittal, ABenchmarking Graphics Benchmark Design and Implementation
Agrawal, AChu, MBranch Prediction Evaluation of Dynamic Branch Prediction Schemes for Deeply Pipelined Superscalar Machines
Stemm, MHarada, DLow Power A Quantative Analysis of Network Interface Power Management in Portable Computers
Pfrommer, BTokuyasu, TBenchmarking Performance measurements of a 3d FFT on a Power2 IBM 590
Cho, FChun, BBenchmarkingMultiscalar Architectures
McGaughy, BChen, JLow Power Low Power Design for Microprocessor
Zhou, MSu, ZBranch Prediction Comparison of Branch Prediction Schemes
Sutton, RJalnapurkar, SNetwork Interfaces Hardware/Software architectures for TCP/IP acceleration for UNIX Workstations
Viswanath, PRajamani, SSpecial Purpose HW Accelerating the RISC processor using Programmable Logic
Fromm, RTabbara, BILP Limits to ILP in the ALPHA microprocessor
Warner, PGalicia, GEmbedded Systems CRISCO (Compressed Reduced Instruction Set COmputing)
Reznik, DNayak, AHW Support for PL Virtual Machine internal organization and its impact on performance